I am currently a Work-Based Learning (WBL) intern at NIELIT Aurangabad through the AICTE internship portal, working in the VLSI design domain. During my internship, I am gaining hands-on experience with EDA tools like Cadence, Synopsys, and Mentor Graphics, focusing on digital VLSI design, physical design, and ASIC Design Flow. I am working on projects related to ASIC/FPGA implementation, which is enhancing my understanding of the complete VLSI design flow.